Implementation of the Cluster Counting and Timing technique on FPGA for the reduction of transferred data and stored information

Ultra-low mass and high granularity Drift Chambers fulfill the requirements of tracking systems for modern High Energy Physics experiments at future high luminosity accelerators (FCC or CEPC). The application of the Cluster Counting/Timing (CCT) technique adds a valuable particle identification capabilities with resolutions outperforming the traditional dE/dx technique. By measuring the arrival times of each individual ionization electron to the sense wire and by using suitable statistical tools it is possible to perform a bias free estimate of the impact parameter and a precise particle identification in drift chamber operating in a Helium based gas mixtures. The CCT technique consisting in identifying pulses due to different ionization electrons and in associating them in clusters according to their relative time delays, therefore it is necessary to have read-out interfaces capable of processing such high speed signals. This requires a data acquisition chain, able to manage the low amplitude signals from the sense wires (a ~few mV) with a high bandwidth (~1 GHz). Requirements on the drift chamber performance impose analog-to-digital conversions by a fast ADC at sample rates of at least 2 GS/s with 14-bit resolution. These constraints, together with maximum drift times and many readout channels, impose some sizeable data reduction strategy, while preserving all relevant information. Measuring both the amplitude and the arrival time of each peak in the signal associated to each ionization electron is the minimum requirement on the data transfer for storage to prevent any data loss. An electronic board including a Fast ADC and an FPGA for real-time processing of drift chamber signals is presented. The implementation of different algorithms for peaks finding are compared.